Holiday closure

Winter Break: Monday, December 23 through Wednesday, January 1
Wright State University administrative and academic offices will be closed.

Digital Integrated Circuit Design with PLDs & FPGAs Lab

Course Type: 
CEG
Code: 
4324L
Credit Hours: 
1
Schedule Type: 
Lab
Prerequisites: 

(Undergraduate level EE 2000 Minimum Grade of C and Undergraduate level EE 2000L Minimum Grade of C and Undergraduate level EE 3210 Minimum Grade of C) or Undergraduate level CEG 3320 Minimum Grade of D

Corequisites: 

CEG4324